1. Field of the Invention
The subject invention relates generally to the design and fabrication of semiconductor devices and, more particularly, to the design and fabrication of a semiconductor nonvolatile memory (NVM) cell, wherein the NVM cell incorporates a thin film of charge-storage material for the retention of data.
2. Related Art
Semiconductor NVMs, and particularly electrically erasable, programmable read-only memories (EEPROMs), exhibit widespread applicability in a range of electronic equipments from computers, to telecommunications hardware, to consumer appliances. In general, EEPROMs serve a niche in the NVM space as a mechanism for storing firmware and data that must be refreshed periodically in situ. The EEPROM""s precursor, the EPROM, can be erased only through UV irradiation and therefore requires removal from its target system prior to erasure. The flash EEPROM may be regarded as a specifically configured EEPROM that may be erased only on a global or sector-by-sector basis. The typical flash EEPROM may be divided into sectors of 64K (65, 536). The sacrifice in flash EEPROM erase selectivity is exchanged for a simplified memory cell design, which, in the limit, may require only a single MOS transistor.
As is well known to those skilled in the art, NVM cells are typically constructed by forming a field effect transistor (FET) in a body of semiconductor material, usually silicon. The FET can be made to store electrical charge (holes or electrons) in either a separate gate electrode, referred to as a floating gate, or in a dielectric layer underneath a control gate electrode. Data is stored in an NVM cell by modulating the threshold voltage, VT, of the FET through the injection of charge carriers from the channel of the FET. For example, with respect to an N-channel, enhancement-mode FET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the FET to exhibit a relatively high VT. When the FET control gate is biased to the voltage required to read stored data, i.e., to a xe2x80x9cReadxe2x80x9d voltage, the FET will fail to conduct current because its then-existing threshold voltage is greater than the voltage applied to the gate. The nonconductive state of the FET may, by convention, be defined and detected as a logic level ZERO. Conversely, a reduction in the concentration of electrons in the floating gate, or in the dielectric layer, will cause the FET threshold voltage to diminish, and, in some designs, become negative with respect to ground. In this case, applying the Read voltage to the FET control gate will cause the FET to conduct current from drain to source. In some designs, the FET VT may be made negative so that an applied Read voltage of 0V will nonetheless be sufficient to cause current conduction by the FET. Current conduction by the FET may be defined and detected as a logic level ONE.
The EEPROM is encountered in numerous configurations. In general, those configurations may be classified according to (i) the nature (i.e., thickness and composition) of the layer used to store charge for VT modulation and (ii) the number of operative gate electrodes available to control the operation of the NVM cell. In particular, a floating-gate NVM cell is characterized by a stacked gate construction in which a floating gate, typically formed from polysilicon, is separated from the substrate by a first (lower) oxide layer and is separated from a polysilicon control gate by a second (upper) oxide layer. No direct electrical connection is made to the floating gate (hence, xe2x80x9cfloatingxe2x80x9d). A split-gate NVM cell typically exhibits two distinguishable channel regions, respectively controllable by the floating gate and the control gate, which are only partially overlapping. A discussion, not purported to be exhaustive, of known NVM configurations follows.
FIG. 1 depicts the more or less canonical configuration corresponding to a floating-gate tunnel oxide (Floating-Gate) NVM cell. The Floating-Gate cell includes a relatively thin tunneling oxide 102 interposed between a doped polysilicon floating gate 104 and a silicon substrate 100. Tunneling oxide 102 is typically thermally grown on substrate 100 to a thickness of approximately, for example, 100 angstroms. The Floating-Gate cell further includes an oxide layer 106 overlying floating gate 104 and underlying a doped polysilicon control gate 108. Fabrication of the Floating-Gate cell may involve successively forming layers 102, 104, 106, and 108 above silicon substrate 100. Portions of the layers not masked by a patterned photoresist layer are etched away to form the stacked structure shown in FIG. 1. A heavily concentrated dopant distribution that is self-aligned to the opposed sidewalls of the stacked structure may then be forwarded into substrate 100 to form source 110 and drain 112. An oxide layer 114 may be thermally grown upon the perimeter of the stacked structure and upon exposed regions of substrate 100 that overlie source 110 and drain 112. Due to exposure to thermal energy during this process, impurities implanted in source and drain regions 110 and 112 undergo lateral migration toward the channel region underneath tunneling oxide 102, resulting in the configuration depicted in FIG. 1.
In subsequent processing, control gate 108 will be coupled to a word line conductor. Bit line conductors can be formed within contact windows of oxide layer 114 for electrical connection to drain region 112. In one approach, floating gate 104 can be programmed by grounding source 110 and drain 112 and applying a relatively high voltage to control gate 108. During programming, electrons from the device substrate pass through tunneling oxide 102 into floating gate 104 by a tunneling mechanism known as Fowler-Nordheim tunneling. Those acquainted with semiconductor device physics understand Fowler-Nordheim tunneling as an instantiation of the quantum mechanical prediction that an electron will pass from the conduction band of one silicon region to that of another silicon region through an intervening silicon dioxide barrier, notwithstanding that such a travel is forbidden by notions of classical physics. See R. H. Fowler and L. Nordheim, xe2x80x9cElectron Emission in Intense Electric Fields,xe2x80x9d Proc. Roy.Soc. London, A119, 173 (1928).
As electrons accumulate in floating gate 104, the accelerating electric field diminishes and the flow of electrons to floating gate 104 decreases. Programming of the memory cell is performed for a time that is sufficient to store a desired level of charge in the floating gate. Discharge of floating gate 104 to erase the cell can be achieved by grounding control gate 108, substrate 100, and source region 110 and applying a relatively high voltage to drain region 112.
Specifically, in order to program (write date to) the exemplary Floating-Gate cell depicted in FIG. 1, a voltage equal to approximately 20 volts (V) is applied to the control gate of the FET, while the drain is grounded. Current flows from the drain and through the channel so that electrons are injected through the oxide layer into the floating gate. As indicated above, electron injection occurs in this manner in accordance with Fowler-Nordheim tunneling effect. Injected electrons accumulate in the floating gate, causing the VT of the FET to increase and the intensity of the electric field between the gate and drain of the FET to increase.
In order to erase data previously written to the Floating-Gate EEPROM, the FET source, drain and substrate are grounded. A reverse bias of 20V is supplied to the control gate. Electrons that had accumulated in the floating gate during the immediately preceding programming operation flow to the substrate through the tunnel oxide layer 102, again in accordance with Fowler-Nordheim effects. As electrons vacate the floating gate, the FET VT decreases, as does the intensity of the electric field between the drain and the control gate.
The Floating-Gate cell structure, as described above, is seen to require the application of relatively high voltages (e.g., 20V) during both programming and erase operations. As a sequela to the requirement for high voltages and high currents, Floating-Gate cell characteristics, in general, and the integrity of the tunnel oxide, in particular, tend to rapidly suffer degradation. Furthermore, largely due to the necessity to generate substantial substrate current, erasure of data from a Floating-Gate cell is not directly available using a 5V supply.
Proceeding now to FIG. 2, depicted there is an NVM cell similarly predicated on a floating-gate construction. However, in contradistinction to the Floating-Gate device of FIG. 1, the NVM cell depicted in FIG. 2 relies on a thin film of, for example, silicon nitride for charge storage and data retention. The nitride film is sandwiched between two oxide layers and the resultant multilayered structure is disposed on a semiconductor substrate. The oxide-nitride-oxide (ONO) stack is then clad with an uppermost layer of polysilicon. Hence, the acronym applied to this form of thin-film, floating-gate NVM construction is SONOS.
As seen in FIG. 2, in a typical embodiment, the SONOS NVM cell comprises a P-type substrate 115 in which there are formed an N+ drain 116 and an N+ source 117. Above the channel region between drain 116 and source 117, there is deposited a layer 118 of silicon dioxide, preferably between 20 and 100 angstroms in thickness, forming an electrical isolation over the device channel. On top of silicon dioxide layer 118 is a silicon nitride layer 120, preferably approximately 100 angstroms thick. The silicon nitride layer represents the memory retention layer of the SONOS cell, serving to trap hot electrons that are injected into the nitride layer. Another layer of silicon dioxide 122 is formed over the silicon nitride layer, preferably to a thickness of approximately 50-100 angstroms. Silicon dioxide layer 122 functions to electrically isolate a conductive gate 124 formed over the silicon dioxide layer 122. The layer forming the gate 124 typically is constructed from polysilicon. The SONOS cell is programmed and erased in a manner similar to the programming and erasing of the memory cell of FIG. 1.
FIG. 3 depicts, in detailed form, an example of an NVM cell that adopts a thin-film split-gate construction to effect source-side hot-carrier programming. A thorough description of the NVM device, including the design, fabrication, and operation thereof, may be had from U.S. Pat. No. 5,8247,584, Method of Making and Accessing Split Gate Memory Device, and U.S. Pat. No. 5,696,383, Split-Gate Memory Device and Method for Accessing the Same, each assigned to the assignee of this patent application and hereby incorporated by reference in its respective entirety.
As may be seen in FIG. 3, the split-gate, thin-film NVM cell 20 is formed on a body of semiconductor material, such as substrate 21, having a top or major surface 212. A select gate structure 215 includes a dielectric layer 214 overlying substrate 21 and a select gate 216 over the dielectric layer. Select gate 216 has sidewalls 217 and 218 opposite each other. By way of example, dielectric layer 214 may be a thermally grown silicon dioxide layer having a thickness between approximately 3 nanometers (nm) and 20 nm. Select gate 216 may be formed by depositing and patterning a conductive layer over a dielectric layer 214. Preferably, the conductive layer consists essentially of a polysilicon layer having a thickness between, for example, approximately 150 nm and 300 nm and is deposited over dielectric layer 214 using a chemical vapor deposition (CVD) process. Further, select gate 216 is preferably doped with ions of an N conductivity type, e.g., phosphorus or arsenic ions, either during a CVD process or during a subsequent doping step.
A drain region 222 is aligned with sidewall 217 of the select gate. By way of example, a self-aligned ion implantation process, which implants ions of N conductivity type, such as, for example, phosphorous or arsenic ions, into substrate 21 is used to form the drain region. Preferably, the ion implantation process is performed through a pad dielectric layer overlying major surface 212 of the substrate. The pad dielectric layer can be dielectric layer 214, a sacrificial oxide layer (not shown), or the like.
A dielectric layer such as, for example, a silicon dioxide layer 223 overlies portions of major surface 212 adjacent sidewalls 217 and 218 of select gate 216. Preferably, silicon dioxide layer 223 has a thickness between, for example, approximately 5 nm and 15 nm and may be formed using a thermal oxidation process or a deposition process. The thermal oxidation process also oxidizes select gate 216 along sidewalls 217 and 218. Therefore, silicon dioxide layer 223 is also formed along sidewalls. In one embodiment, portions of dielectric layer 214 that are left unprotected by select gate 216 are etched away before forming silicon dioxide layer 223 on a major surface 212. In another embodiment, silicon dioxide layer 223 is formed on the portions of dielectric layer 214 that are unprotected by select gate 216. A silicon nitride layer 224 having a thickness between, for example, approximately 5 nm and 15 nm overlies silicon dioxide layer 223. Silicon nitride layer 224 is preferably formed with a CVD process. Another dielectric layer, such as, for example, a silicon dioxide layer 228 having a thickness between approximately 5 nm and 15 nm overlies silicon nitride layer 224. Silicon dioxide layer 228 can be formed using a chemical vapor deposition process.
Silicon dioxide layer 223, silicon nitride layer 224, and silicon dioxide layer 228 form an oxide-nitride-oxide (ONO) stack, which is also referred to as a dielectric stack. In ONO stack 225, silicon dioxide layer 223 is referred to as a bottom dielectric layer, and silicon dioxide layer 228 is referred to as a top dielectric layer. When programming NVM cell 20, charge carriers, e.g., electrons, are injected into ONO stack 225 and are trapped in charge-trapping sites formed in silicon nitride layer 224. In order for NVM cell 20 to manifest an acceptable data retention rate, bottom dielectric layer 223 and top dielectric layer 228 are preferably optimized.
A control gate 232 overlies ONO stack 225. Control gate 232 has a sidewall 231 adjacent select gate 216 and has a sidewall 233 opposite to sidewall 231. By way of example, control gate 232 is formed by depositing and patterning a conductive layer over ONO stack 225. Preferably, the conductive layer is a polysilicon layer having a thickness between, for example, approximately 200 nm and 300 nm. The conductive layer is deposited over ONO stack 225 using a CVD process. In other words, control gate 232 is preferably formed as a polysilicon silicon sidewall spacer adjacent select gate 216. Further, control gate 232 is preferably doped with ions of N conductivity type, e.g., phosphorus or arsenic ions, either during the CVD process or during a subsequent doping step. It should be noted that the process of forming control gate 232 also forms a polysilicon sidewall spacer (not shown) along sidewall 217 of select gate 216. However, the polysilicon silicon sidewall spacer along sidewall 217 of select gate 216 does not participate in the operation of the NVM cell. In one embodiment, the vestigial sidewall spacer is removed in subsequent etching step, resulting in an NVM cell as shown in FIG. 3. In another embodiment (not shown), the polysilicon sidewall spacer is coupled to a reference voltage level, e.g., a ground voltage level, during the operation of accessing the NVM cell.
Dielectric spacers, such as, for example, nitride spacers 234 and 235, are formed along sidewall 233 of control gate 232 and along sidewall 217 of select gate 216, respectively. Preferably, a nitride spacer 234 covers control gate 232. Source region 236 is aligned with nitride spacer 234. By way of example, a self-aligned ion implantation process, which implants ions of N conductivity type, such as, for example, phosphorus or arsenic ions, into a substrate 21 is used to form source region 236. Source region 236 and drain region 222 define a channel region 238 therebetween. That is to say, a channel region 238 separates source region 236 from drain region 222 by a predetermined distance. A first portion of channel region 238 is positioned under ONO stack 225 and control gate 232; and a second portion of a channel region 238 is positioned under select gate structure 215. It should be understood that nitride spacers 234 and 235 are optional in the NVM cell. In an alternative embodiment, in which the NVM cell does not include nitride spacers 234 and 235, source region 236 is aligned with sidewall 233 of a control gate 232.
It should be noted that the processes of forming an ONO stack 225 over major surface 212 also forms an ONO stack on top of select gate 216 (not shown). The ONO stack on top of select gate 216 and portions of the ONO stack 225 (not shown) on major surface 212 that are unprotected by nitride spacers 234 and 235 are removed in an etching process.
A silicide structure 242 overlies select gate 216 and functions as the select gate electrode of the NVM cell. Likewise, a silicide structure 244 overlies source region 236 and functions as the source electrode of the NVM cell. In addition, a silicide structure 246 overlies a drain region 222 and functions as a drain electrode of the NVM cell. Silicide structures 242, 244, and 246 are aligned with nitride spacers 234 and 235. Thus, those structures are also referred to as self-aligned silicide (salicide) structures. Silicide structures reduce the parasitic resistance in the NVM cell and, therefore, improve the performance of the cell. However, it should be noted that silicide structures are optional features in the NVM cell.
Notwithstanding the advantages directly associated with the NVM gate structure depicted in FIG. 3 and described herein immediately above, it has been recognized that certain additional advantages may be realized through the implementation of an NVM gate structure that has not been heretofore disclosed or suggested. In a manner that will be made fully apparent below, the subject split-gate, thin-film storage NVM cell structure retains, or improves upon, device fabrication simplicity and economy. In addition, the salient features, advantages, and capabilities of the invention include improved uniformity among the NVM cells and mitigation of over-erase problems attendant some NVM cell configurations. Furthermore, the steps necessary to erase NVM cells are less stringent, and data retention by programmed NVM cells is improved. Also, the subject NVM cell is amenable to source-side hot-electron injection programming and source-side hot-hole injection erasure.
The above and other features, advantages and capabilities are realized in one aspect of the invention by a semiconductor device that comprises a semiconductor substrate that has a major, or uppermost, surface. A drain and a source are formed in the substrate of the semiconductor device, defining a channel therebetween. A charge-storage gate dielectric is disposed on the major surface over at least a portion of the source and at least a first portion of the channel. A select gate dielectric is disposed over at least a portion of the drain and a second portion of the channel region. A gate conductor is disposed over both the charge-storage gate dielectric and the select gate dielectric. In one embodiment, the gate conductor is monolithic in form.
A second aspect of the invention inheres in a semiconductor nonvolatile memory (NVM) cell. The NVM cell comprises a semiconductor body having a top surface; a drain formed in the semiconductor body; a source formed in the semiconductor body and spaced apart from the drain by a predetermined distance; a channel occupying at least a portion of the semiconductor body between the drain and the source; a first gate dielectric disposed on the top surface of the semiconductor device over at least a portion of the source; a second gate dielectric disposed on the top surface of the semiconductor device over at least a portion of the drain and juxtaposed to the first gate dielectric so that the first gate dielectric and the second gate dielectric together substantially cover an area of the channel at the top surface; and a gate conductor covering the first gate dielectric and the second gate dielectric.
A third aspect of the invention is apprehended in a gate structure for a nonvolatile memory (NVM) cell. The gate structure comprises a charge-storage gate dielectric, a select gate dielectric, and a monolithic gate conductor disposed over at least substantial portions of both the control gate dielectric and the select gate dielectric.
Another aspect of the invention is found in a semiconductor nonvolatile memory (NVM) dual cell that comprises a body consisting essentially of semiconductor material, the body having: a major surface; a first drain formed in the body of the semiconductor device; a second drain formed in the body of the semiconductor device; a common source formed in the body of the semiconductor device, the common source positioned laterally between the first drain and the second drain; a first channel in the body and defined by the first drain and the common source; a second channel in the semiconductor body and defined by the second drain and the common source; a first select gate dielectric disposed on the major surface over at least a portion of the first drain and at least a first portion of the first channel; a second select gate dielectric disposed over at least a portion of the second drain and a first portion of the second channel; a first charge-storage gate dielectric disposed over at least a portion of the common source, and a second portion of the first channel; and a second charge-storage gate dielectric disposed over at least a portion of the common source and a second portion of the second channel.
Accordingly, a corresponding aspect of the invention subsists in a method of operating a semiconductor nonvolatile memory (NVM) cell that is constructed to include (i) a drain and a source formed in a semiconductor substrate; (ii) a channel extending between the drain and the source and consisting essentially of a first channel portion proximal to the source and a second channel portion proximal to the drain; (iii) a charge-storage gate dielectric in the form of an ONO stack disposed over at least a portion of the source and the first channel portion and comprising a bottom insulating layer, an intermediate charge-storage layer, and a top insulating layer; (iv) a select gate dielectric consisting essentially of a single insulating layer; and (V) a gate conductor covering the control gate dielectric and the select gate dielectric. The cell is programmed by applying a programming row-select voltage to the gate conductor, applying programming a column-select voltage to the drain, and applying a programming bias voltage to the source so as to cause source-side hot-electron injection into the charge-storage layer of the ONO stack. The NVM cell is erased by applying an erase row-select voltage to the gate conductor, applying a first erase bias voltage to the substrate, and applying a second erase bias voltage to the source so as to cause source-side BTBT-induced hot-hole injection into the charge-storage layer of the ONO stack. The NVM cell is read by further applying a read row-select voltage to the gate conductor, applying a read column-select voltage to the drain, and applying a read bias voltage to the source so as to cause current to flow from the drain to the source of the NVM cell.
In a related aspect, the invention may be practiced as a fabrication process for a split-gate thin-film storage NVM cell. In accordance with the process, a semiconductor substrate of a predetermined first conductivity type is provided, on which substrate are successively formed a bottom insulating layer, an intermediate charge-storage layer, and a top insulating layer. A charge-storage gate dielectric stack is patterned from the above layers over a first portion of the semiconductor substrate. Then an impurity, of the same conductivity type as the substrate, is implanted into a second portion of the substrate. A select gate dielectric insulating layer is formed over the semiconductor substrate so that this insulating layer abuts, or is contiguous to, the charge storage-gate dielectric stack. A monolithic (polysilicon) gate conductor is deposited over the charge-storage gate dielectric stack and the select gate dielectric. An etching step is then applied to (i) a first portion of the gate conductor and a portion of the charge-storage dielectric stack (thereby forming a first sidewall) and (ii) a second portion of the gate conductor and a portion of the select gate dielectric (thereby forming a second sidewall). Exposed areas of the semiconductor substrate are implanted with an impurity of a conductivity type that is opposite to the conductivity type of the impurity earlier implanted. This implantation results in the formation of a source region that subtends at least a portion of the charge-storage gate dielectric stack and a drain region that subtends at least a portion of the select gate dielectric.